A) Field of the Invention
The present invention relates generally to a low dielectric constant insulator having a low specific dielectric constant, a method of growing a low dielectric constant insulating layer, a semiconductor device having a low dielectric constant insulating layer, and a method of manufacturing a semiconductor device having a low dielectric constant insulating layer. The invention relates specifically to a low dielectric constant insulator suitable for use with a semiconductor integrated circuit having multi-layer wirings, a method of growing a low dielectric constant insulating layer, a semiconductor device having multi-layer wirings and low dielectric constant insulators, and a method of manufacturing such a semiconductor device.
B) Description of the Related Art
Semiconductor integrated circuit devices are becoming highly integrated, and there is the tendency that the scale of wirings of each device increases one generation after another. As the wiring scale becomes large, the number of wiring layers increases so that a multi-layer wiring structure is adopted. High integration of a semiconductor integrated circuit device results in a narrow wiring space.
There is the tendency that the wiring space is narrowest at lower level wiring layers and broadens toward upper level wiring layers. Many of lower level wirings are used for transmitting signals, whereas many of upper level wirings are used for power source lines. Because of this characteristic difference, the conditions required for multi-layer wirings are not the same.
A transmission speed of a signal in a wiring is governed by wiring resistance and wiring parasitic capacitance. It is desired for a high speed operation to lower a wiring resistance and reduce a wiring parasitic capacitance.
In order to lower a wiring resistance, Cu wirings are used nowadays in place of Al wirings. It is difficult to use wiring material having a resistivity lower than that of Cu. As the reduction in a wiring resistance reaches near its limit, it becomes necessary to reduce a wiring parasitic capacitance. When Cu wirings are used, a diffusion preventive film of SiN, SiC or the like is formed covering each Cu wiring in order to prevent oxidation and diffusion of Cu.
A parasitic capacitance between wirings increases if the wiring space becomes narrow assuming the same wiring thickness. The influence of a parasitic capacitance upon a device operation speed is small if the device has a wiring space of 1 μm or broader, whereas this influence becomes large if the device has a wiring space of 0.5 μm or narrower. It can be expected that if a device has a wiring space of 0.2 μm or narrower, the parasitic capacitance greatly influences the device operation speed.
The parasitic capacitance between wirings can be reduced if the wiring thickness is made thin and the confronting area of adjacent wirings is made small. However, as the wiring thickness is made thin, the wiring resistance increases so that the operation speed as a whole cannot be improved.
The most effective means for reducing the wiring parasitic capacitance is to make an insulating layer between wirings have a low dielectric constant. Insulating materials having a lower specific dielectric constant have been used in place of silicon oxide (USG) having a specific dielectric constant of about 4.1, P-doped silicon oxide (PSG) and B- P-doped silicon oxide (BPSG).
Other materials now in use include: organic insulating materials having a very low specific dielectric constant (such as SiLK (registered trademark) and FLARE (registered trademark)); and porous materials such as porous silicon oxide. These materials have characteristics largely different from those of silicon oxide and are difficult to be used as the material of an interlayer insulating film for multi-layer wirings because of their mechanical strength, reliability and the like. These materials are therefore used mainly for lower level wiring layers.
Silicon oxycarbide (SiOC) has been paid attention as another insulating material having a low specific dielectric constant. A vapor-grown silicon oxycarbide film available from Novellus Systems, Inc., called CORAL (registered trademark), is manufactured at a deposition speed of about 1000 to 1200 nm/min by plasma enhanced chemical vapor deposition (CVD) under the conditions of source gas of tetramethylcyclotetrasiloxane (TMCTS), oxygen (O2) and carbon dioxide (CO2), a flow rate TMCTS:O2:CO2=5:250:5000 (ml/min, sccm), a gas pressure of 4 torr, an HF (13.56 MHz) power of 600 W and an LF (1 MHz or lower) power of 400 W.
This insulating material called CORAL has Si—O—C as its main skeleton and a specific dielectric constant of 2.9 which is considerably lower than that of silicon oxide. This insulating material is promising as an interlayer insulating layer material for multi-layer wirings.
It has been proposed that a silicon oxycarbide layer is used partially as a hard mask layer and thereafter the silicon oxycarbide layer is left as a portion of an interlayer insulating film having a low dielectric constant (refer to Japanese Patent Laid-open Publication No. 2003-218109, family of U.S. patent application Ser. No. 10/053,288 filed on Jan. 17, 2002).
A low specific dielectric constant material is generally has low adhesion to, for example, an underlying layer formed as a diffusion preventive film for Cu. If the number of wiring layers is increased by using interlayer insulating films having low adhesion, a film peel-off occurs at the interface to the underlying layer.
It is desired that the multi-layer wiring structure uses a lamination of a plurality of low dielectric constant insulating layers having different thermal expansion coefficients. The material having a low specific dielectric constant has generally the tendency of a low density and a low mechanical strength. If there exists a mismatch of a thermal coefficient between interlayer insulating layers, a large stress is generated at the interface so that cracks may be formed in the insulating layer having a low relative dielectric factor.